1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and relates in particular to a semiconductor integrated circuit device having a high speed clock distribution network. This invention further relates to a technology capable of a high speed clock distribution network that efficiently utilizes design resources of independently designed semiconductor circuits.
2. Description of Related Art
FIG. 2 shows an example of a semiconductor integrated circuit device utilizing a high speed clock distribution network of the prior art. In the figure, the reference numeral 101 denotes a phase locked loop (PLL), 102 is a clock distribution line and 103 is a clock buffer. Reference numeral 120 denotes an input clock which is multiplied (increased) N times by the PLL 101 and output frequency to 102 as a multiplied (increased) by N times. The clock pulse multiplied by PLL 101 is amplified in 103 and distributed to each latch (latch and flip-flops are different from each other in the strict sense of the word, however here both latch and flip-flops are represented by the word xe2x80x9clatchxe2x80x9d) with an equivalent delay. Technical features assuring an equal-length wiring are utilized in order to achieve an equivalent distributed delay.
Once of the distributed clocks 104 is input to the PLL 101 and the PLL 101 functions to obtain an identical phase for the clocks 104 and 120.
FIG. 3 shows the clock distribution network for the semiconductor integrated circuit device of FIG. 2 when added with a macro 130a and 130b. A macro is a separately designed circuit that satisfies specifications for circuits other than the macro (hereafter referred to as mother circuits) as well as interface specifications between macro and mother circuit. As long as these interface specifications are satisfied, the macro can change the mother circuit in various ways.
As one example, the DRAM macro has a memory function to store information by means of capacitance in a circuit described in the 1998 IEEE International Solid-State Circuit Conference Digest of Technical Papers, pp. 72-73.
These macro circuits are sometimes designed as separate items by different designers. One designer may specialize in DRAM macro design while another may specialize in coprocessor macro design. A circuit can then be systematically assembled by combining the macros obtained from these different sources. This method allows utilizing existing macros to design system-level integration devices with high additional value.
In the macro, software IP is used to show design data at the circuit level, and hardware IP is data listing the physical structure of the semiconductor integrated circuit device such as the layout. Hardware IP is more appropriate when high speed operation is required, because performance cannot otherwise be guaranteed when redrafting the physical layout of the circuit.
The clocks distributed to the mother circuit latches are also supplied at an identical phase to the latches in the circuits 121 and 122. The respective macros 130a and 130b distribute the clock pulses input from 121 and 122 to the latches within each macro at an equivalent delay by utilizing the clock buffers 133a and 133b within each macro.
The clock distribution in the semiconductor integrated circuit device of FIG. 3 containing the macros is at a phase identical to the clock phase of 121 and 122 and the latch phase within each mother circuit. However, a delay time Tm is required from 121 and 122 to the input of the clocks to the latches within each macro so that a phase difference (skew) equivalent to the Tm, occurs between the latches within the mother circuit and the latches within the macros.
Further, the Tm within each macro is different so that skew also occurs between macros. This Tm tends to become large when using large scale macros (also called megacells) and the clock skew increases in the semiconductor integrated circuit device using these macros.
In the semiconductor integrated circuit devices of the prior art containing these macros, skew occurs between the clock pulses supplied to the latches within the mother circuit and the clock pulses supplied to the latches within the macro. These clock skews interfere with the high frequency function of the semiconductor integrated circuit device clock frequency so that the semiconductor integrated circuit device cannot be operated at high speed.
A proper delay time for the clock distribution network, from the clock buffer 103 to 121 or 122 calculated during the macro design stage, that takes the Tm into account will resolve this problem but has the drawback that macrocell design cannot be performed independently of mother circuit design.
In order to resolve the above mentioned problems, this invention has a clock generator to supply clock signals, a plurality of first controlled circuits supplied by the clock pulses from the clock generator and a phase adjuster for these clock signals, a second controlled circuit supplied by the clock signal that passed through the clock signal phase adjuster, and configured so that the clock phase input to this clock signal phase adjuster and first controlled circuit are an identical phase.
The number of first controlled circuits supplied at this time by clock pulses from the clock generator is typically larger than the number of clock signal phase adjuster (circuits).
This invention in this case, is characterized in having a clock generator to supply clock signals, a plurality of first controlled circuits supplied by the clock pulses from the clock generator and a phase adjuster for these clock signals, a second controlled circuit supplied by the clock signal that passed through the clock signal phase adjuster, and further characterized in that the number of the plurality of first controlled circuits supplied by clocks from the clock generator is larger than the number of clock signal phase control circuits.
To restate, this invention is characterized in that the percentage shared by first control circuits from among the fan-out of the clock generator is larger than the percentage of clock signal phase control circuits.
A phase adjusting means contains a phase frequency detector to compare the frequencies input with the first clock and the second clock, and is configured to output the three clock signals controlled by the output of the phase frequency detector.
In a more detailed description, the semiconductor integrated circuit device of this invention has a first clock processing means to input a first clock and a second clock and generate a third clock, a second clock processing means to input a third clock and a fourth clock and generate a fifth clock, and a first latch group and a second latch group comprised of at least one latch, wherein the second clock is generated from the third clock by way of a buffer, the frequency of the second and third clocks are identical, the first clock processing means generates the third clock so that the first and second clocks will have an identical phase and frequency, a fourth clock is generated by way of a buffer from the fifth clock, the frequency of the fourth and fifth clocks are identical, the second clock processing means generates a fifth clock so that the third and fourth clocks will have an identical phase and identical frequency, the third clock is supplied by way of a buffer to the first latch group, the fifth clock is supplied by way of a buffer to the second latch group, and the first latch group and the second latch group operate at an identical phase.
Phrases such as xe2x80x9cidentical phase, identical frequencyxe2x80x9d as related in these specifications, allow for an error of an extent that can be ignored without hindrance to actual operation and can be tolerated in terms of performance demanded of the circuit.
The first clock processing means of this invention as described in a more detailed example, consists of a phase frequency detector to input a first clock and a second clock and output a first error signal, a charge pump circuit to input a first error signal and output a second error signal, a low-pass filter to input a second error signal and output a third error signal, and a voltage-controlled oscillator to change the oscillator frequency according to the third error signal. The third clock is capable of being generated by the voltage-controlled oscillator.
This invention is especially effective when making a single circuit such as semiconductor integrated circuits (chips) by combining a plurality of circuits from different sources (different designers and design companies).
In other words, a circuit design method for reading out a first circuit block of design data from a recording medium in which is stored the first circuit block of design data, and integrating this with a second circuit block of design data as design data for a signal semiconductor integrated circuit device and characterized in that a phase adjuster means inserts a clock signal between the first circuit block and the second circuit block. Utilizing this circuit design method eliminates the problem of clock phase deviations throughout the entire circuit.
A circuit design method to prepare design data for a first circuit block having a clock output terminal to output a clock signal, and having a circuit to adjust the phase of the clock signal sent from the clock output terminal, and combined with design data for a second circuit block, wherein the clock output terminal of the first circuit block is connected to the clock input terminal of the second circuit block. Utilizing this method, a clock phase correction means is prepared beforehand for the circuit forming the mother circuit so that the load imposed is reduced when circuits are combined.
In a separate configuration, a clock phase adjuster means can be internally incorporated onto the circuit block that is to be added. By distributing design data for this kind of circuit, the purchaser can join and integrate circuits to achieve a circuit system of high additional value without having to worry about clock deviations between circuits.
This kind of design data is characterized in that it can be stored on a record medium such as a CD-ROM that stores circuit design data such as for circuits having a clock input terminal for receiving clock signals, circuits to adjust the clock signal phase sent from the clock input terminal, and internal circuits controlled by the adjusted clock signals. This circuit design data can then be distributed while stored on the CD-ROM.
For design data, a variety of items (so-called software IP) are available to show circuit electrical connections (so-called circuit schematics) or items (so-called hardware IP) such as to show physical scales, layouts, and material specifiers are available when the actual semiconductor integrated circuit device has been achieved. The data may be shown numerically or in a graphical form.
The circuits described with this kind of design data often describe only a portion of a single circuit device (such as a chip) however the signal exchange with external circuits is mostly performed by the metal level formed on the board substrate. The data for these portions of the circuit can be confirmed using hardware IP.
Instead of distributing this kind of data by CD-ROM as previously mentioned, the Internet can be used. In such cases, a recording medium to store circuit design data such as for circuits having a clock input terminal for receiving clock signals, circuits to adjust the clock signal phase sent from the clock input terminal, and internal circuits controlled by the adjusted clock signals, can be prepared beforehand and when data transfer is requested by a user, the circuit data stored on the recording medium can be sent to the user. If progress is made on setting up a proper infrastructure, then the Internet distribution method may prove more convenient than distribution by CD-ROM.
The main means utilized in this invention for resolving the above mentioned problems in the semiconductor integrated circuit device are a first clock processing means to input a first clock and a second clock and generate a third clock so that the first and second clocks will have identical phases and identical frequencies, a second clock processing means inputs a third clock and a fourth clock and generates a fifth clock so that the third and fourth clocks will have identical phases and identical frequencies, and a first latch group and a second latch group comprised of a plurality of latches wherein a second clock is generated from a third clock by way of a buffer or divider, a fourth clock is generated from a fifth clock by way of a buffer or divider, the third clock is supplied by way of a buffer to the first latch group and the fifth clock is supplied by way of a buffer to the second latch group.